Several leadframe packages having an industry standard pin layout and specified length and width are commonly used to house DRAM devices. The packages comprise a leadframe having a plurality of leads that serve as support for the semiconductor chip. Bonding wires connect the bonding pads of the chip to interconnecting leads of the leadframe that protrude on opposing sides from the molding compound and allow data transfer of the chip with an external device. The wire bonds are typically thin gold wires having a significant inductance. Therefore, layouts are preferred in which the distance between the leadframe terminals and the bonding pads of the chip is minimized.
Typically the bonding wires are located close to the interconnecting leads on opposing sides of the package. Therefore, the length of the side of the chip extending orthogonally to the opposing sides of the package where the interconnecting leads are located is limited. Since the chip size determines the data storage capability of the chip, the data storage capability is also limited. U.S. Patent Publication No. 2004/0212053 A1, which is incorporated herein by reference, discloses an arrangement, wherein the bond pads of the chip are located on a centerline on a surface of the chip. The centerline bond pads are re-distributed by a re-distribution layer on the surface of the chip. The ending locations of the fan-out pads of the redistribution layer are chosen to match with the leadframe terminal.
What is desired is a semiconductor device based on lead-on-chip architecture and a method for fabricating thereof, in which the arrangement of the bond pads of a chip and the corresponding terminal leads of a leadframe allows fitting in bigger chips into the semiconductor device, wherein the process for fabricating the semiconductor chip is a fast and low-cost process.